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[AK7734] ms1033-e-02-pb - 1 - 2010/01 general description the AK7734 is a highly integrated audio digital signal pr ocessor with integrated 2ch 24bit adc and 2ch src. it includes internal memories for digital audio processing, that allows surround effect process, time alignment and parametric equalizing. more over, the AK7734 can proc ess both data and filter coefficients as floating point data so that high accuracy iir/fir filter per formance can be achieved easily. the internal src has various sampling rate converting modes, correspo nds many sampling rates without changing the dsp operating sampling frequency. the AK7734 can operate a hands-free software by akm, as well as sound processing, by programs downloaded vi a the microprocessor interface. features [dsp block] - word length: 24bit (coefficient ram & data ram: f24 floating point) - processing speed: 13.6 ns (1536step/fs; fs = 48khz) - multiplication: 20 x 24 44-bit double precision arithmetic available - divider 20 / 20 20bit - alu: 48bit arithmetic operation (overflow margin 4bit) 20bit floating point arithmetic and logic operation - program ram: 3072 x 24bit - coefficient ram: 2048 x 24bit (f24 floating point) - data ram: 2048 x 24-bit (f24 floating point) - offset register: 64 x 13bit - delay ram1: 3072 x 24-bit - delay ram2: 2048 x 24-bit - sampling rate: fs= 7.35k ~ 48khz - master clock: 1536fs (generated from 32fs, 48fs, 64fs, 128f s, 256fs, 384fs by internal pll) - master/slave operation [adc block] - 64 times over sampling - 24bit 2ch - sampling rate: 7.35 ~ 48khz - s/(n+d): 83db (fs = 48khz) - dr, s/n: 96db (fs = 48khz) - integrated dc offset can celing high pass filter [src block] - 2ch x 1 system - support frequency: fin = 7.35khz ~ 96khz fout = 7.35khz ~ 48khz (fso/fsi = 0.167~ 6.0) [digital interface input/output] - 8ch serial data input - 8ch serial data output audio dsp with 2-channel adc/src AK7734
[AK7734] ms1033-e-02-pb - 2 - 2010/01 [micro computer interface] - i 2 c interface or 4-wired interface [general] - integrated pll - integrated regulator 3.3v 1.8v - power supply: 3.3v 0.3v - operating temperature range: -40 ? c ~ 85 ? c - 48pin lqfp
[AK7734] ms1033-e-02-pb - 3 - 2010/01 block diagram figure 1. block diagram * figure 1 shows a simplified diagram of the AK7734, which is not the perfect same as the actual circuit diagram. xto sdin3 / jx1 sdin2 / jx0 sdin1 pull down vref avdd 1 ainr xti clkgen & cont clko bitclko lrclko lflt initrstn jx1 wd t wdte n 4 ckm[3:0] 4 vs s dvdd 5 clkoe bitclko e lrclko e bitclki1 lrclki1 open drain a dc sdoutad sto din3 lock e din4 din5 din2 jx0 dout4 sdout4 dsp sclk / scl si / cad0 rqn / cad1 so / rdy rdy sda i2csel micif jx1e jx0e out4 e src srcbicki srclrcki bitclki2 lrclki2 ckg srcmcki unlock sdin4 / jx2 srci srco 1 0 setsrc srclflt srcbicko srclrcko seldi4 1 0 seldo 4 mbitclk0 mlrclk0 mdspclk0 madclk0 testi2 dout3 dout2 dout1 sdout3 sdout2 sdout1 out1e out2e out3e seldo1[1:0] seldo2[1:0] seldo3[1:0] ldo testi1 ainl 1 0 so din1 jx2 e jx 2 selrdy rdye 2 0 1 3 gp1 gp0 irp t 2 0 1 3 2 0 1 3 4 avdrv vcom
[AK7734] ms1033-e-02-pb - 4 - 2010/01 cp0,cp1 cram 2048w24-bit dp0,dp1 dram 2048w24-bit mp24 mp20 ofreg 64w13-bit x y multiply 2420 44-bit micon i/f control pram 3072w 36-bit dec pc stack: 5level(max) mul dbus shift a b a lu 48-bit overflow margin: 4-bit dr0 3 over flow data generator division 20 20 20 peak detector serial i/f cbus(24-bit) dbus(24-bit) 44-bit 24-bit 44-bit 48-bit 48-bit dlram1:3072w24-bit ptmp(lifo) 624-bit dlp0,dlp1 di n1 dout4 224,20,16-bit 224,20,16-bit 48-bit dout1 tmp 1224-bit 224,20,16-bit 224(,16)-bit din5 (adc) dout2 dout3 224,20,16-bit 224,20,16-bit di n4 (src) 224,20,16-bit din3 di n2 224,20,16-bit 224(,16)-bit dlram2:2048w24-bit figure 2. main dsp block diagram of the AK7734
[AK7734] ms1033-e-02-pb 5 2010/01 ordering guide AK7734xq -40 +85 c 48pin lqfp akd7734 evaluation board for AK7734 pin layout sda lrclki2 (top view) 48pin lqfp xti lrclki1 xto testi1 v co m avdd bitclki1 a vdrv rqn/cad1 so/rdy jx2/sdin4 ckm [ 0 ] sto 1 12 3 2 5 4 7 6 9 8 10 11 38 37 43 42 41 40 39 47 46 45 44 48 21 20 19 18 17 15 16 23 22 13 14 24 32 30 31 28 29 26 27 35 25 33 34 36 vss2 vss5 lflt srclflt dvdd setsrc a inr initrstn i2csel dvdd jx1/sdin3 vss1 jx0/sdin 2 vss4 dvdd si/cad0 vss3 testi2 a inl ckm [2] ckm [1] sdin1 dvd d sclk/scl bitclki2 sdout3 sdout4 ckm [ 3 ] note) xxxx is internal pull-down pin. xxxx is the pin name. sdout2 sdout1 input output i/o power pin clko bi tcl ko lrclko
[AK7734] ms1033-e-02-pb 6 2010/01 no. name i/o function classification 1 testi1 i test1 pin (internal pull-down) this pin must be connected to vss. test 2 ckm[2] i clock mode select pin2 mode select 3 ckm[1] i clock mode select pin1 mode select 4 sdin1 i serial data input pin1 digital input jx0 i conditional jump pin0 a conditional jump pin (jx0) is available by setting control register (jx0e) to ?1?. conditional input 5 sdin2 i serial data input pin2 digital input jx1 i conditional jump pin1 a conditional jump pin (jx1) is available by setting control register (jx1e) to ?1?. conditional input 6 sdin3 i serial data input pin2 digital input 7 bitclki1 i serial bit clock input pin1 normally connected to the bluetoot h data clock line (256khz/512khz). system clock 8 lrclki1 i lr channel select clock pin1 normally connected to the bl uetooth lr clock line (8khz). system clock 9 dvdd - power supply for digital section 3.0v ~ 3.6v digital power supply 10 vss1 - ground pin 0v power supply 11 xti i crystal oscillator input pin connect a crystal oscillator between this pin and the xto pin, or input an external clock to the xti pin. clock 12 xto o crystal oscillator output pin when a crystal oscillator is used, connect it between xti and xto. when an external clock is used, leave this pin open. during initial reset, the output of this pin is not determinable. clock 13 sdout4 o serial data output pin4 outputs ?l? during initial reset. digital output 14 sdout3 o serial data output pin3 outputs ?l? during initial reset. digital output 15 sdout2 o serial data output pin2 outputs ?l? during initial reset. digital output 16 sdout1 o serial data output pin1 outputs ?l? during initial reset. digital output 17 vss2 - ground pin 0v power supply 18 dvdd - power supply for digital section 3.0v ~ 3.6v digital power supply 19 i2csel i i 2 c bus select pin (internal pull-down) i2csel pin = ?l?: 4-wired interface i2csel pin = ?h?: i2cbus selected mode. scl and sda are active. i2csel should be connected to ?l? (vss) or ?h? (dvdd). i 2 c select 20 initrstn i reset pin (for initialization) use to initialize the AK7734. when changing ckm [3:0] and changing xti or bitclk input frequency, it is necessary to set this pin. reset 21 ckm[0] i clock mode select pin mode select 22 lrclko o lr channel select clock pin outputs ?l? during initial reset in master mode. system clock output pin function
[AK7734] ms1033-e-02-pb 7 2010/01 no. name i/o function classification 23 bitclko o serial bit clock output pin outputs ?l? during initial reset in master mode. system clock output 24 clko o clock output pin outputs ?l? during initial reset. clock output 25 sto o status output pin outputs ?h? during initial reset. status so o serial data output pin for microprocessor interface outputs ?l? during initial reset. microprocessor interface 26 rdy o data write ready output pin for microprocessor interface outputs rdy when selrdy bit = ?1? microprocessor interface 27 lrclki2 i lr channel select clock pin2 (for src) system clock input 28 bitclki2 i serial bit clock input pin2 (for src) system clock input jx2 i conditional jump pin2 a conditional jump pin (jx2) is available by setting control register (jx2e) to ?1?. conditional input 29 sdin4 i serial data input pin4 normally used for src serial data input pin. digital input rqn i microprocessor interface write re quest pin (i2csel pin = ?l?) when initial reset state and microcomput er interface are no t in use, leave rqn pin= ?h?. microprocessor interface 30 cad1 i i 2 c bus address setting pin 1 (i2csel pin = ?h?) i 2 c si i serial data input pin for microp rocessor interface (i2csel pin = ?l?) when si is not used, tie the si pin = ?l?. microprocessor interface 31 cad0 i i 2 c bus address setting pin 0 (i2csel pin = ?h?) i 2 c o i2csel pin = ?l? leave this pin open. sda outputs ?l?. open 32 sda i/o i 2 c bus data clock pin (i2csel pin = ?h?) outputs ?hi-z? during initial reset. i 2 c sclk i serial data clock pin for micropro cessor interface (i2csel pin = ?l?) when sclk is not used, tie the sclk pin = ?h?. microprocessor interface 33 scl i i 2 c bus data clock pin (i2csel pin = ?h?) i 2 c 34 dvdd - power supply for digital section 3.0v ~ 3.6v digital power supply 35 vss3 - ground pin 0v power supply 36 avdrv o avdrv pin connect a 1 f capacitor between this pin and no.35 pin (vss3). no external circuits should be connected to this pin. this pin outputs ?l? during initial reset. analog output 37 srclflt o src, pll rc component connect pin connect a 1 f capacitor between this pin an d vss4. this pin outputs ?l? during initial reset. analog output 38 vss4 - ground pin 0v power supply 39 dvdd - power supply for digital section 3.0v ~ 3.6v digital power supply 40 ckm[3] i clock mode select pin3 mode select 41 setsrc i pll reference clock select pin for src mode select 42 testi2 i test2 pin (internal pull-down) this pin must be connected to vss. test 43 ainr i adc single-ended input pin for rch analog input
[AK7734] ms1033-e-02-pb 8 2010/01 no. name i/o function classification 44 ainl i adc single-ended input pin for lch analog input 45 avdd i analog ground 0v analog power supply 46 vcom o analog common voltage output pin connect 0.1 f and 2.2 f capacitors between this pin and no.47 pin (vss5). no external circuits should be connected to this pin. this pin outputs ?l? during initial reset. analog output 47 vss5 i ground pin 0v power supply 48 lflt o pll rc component connect pin connect c=12nf between this pin and no.47 (vss5). this pin outputs ?l? during initial reset. analog output note: ? do not leave digital input pins open. ? when analog input pins (ainl, ainr ) are not used, leave them open. handling of unused pin the following table illustrates recommended states for open pins: classification pin name setting analog ainl, ainr leave open. sdout1-4, clko, lrclko, bitclko, sto, so/rdy, xto leave open. digital testi1, testi2, sdin1, jx0-2/sdin2-4, xti, bitclki1-2, lrclki1-2 connect to vss.
[AK7734] ms1033-e-02-pb 9 2010/01 (vss1=vss2=vss3=vss4=vss5=0v: note 1 ) parameter symbol min max units power supply voltage analog digital avdd dvdd -0.3 -0.3 4.3 4.3 v v input current (except for power supply pin ) iin ? 10 ma analog input voltage ainl pin, ainr pin vina -0.3 avdd+0.3 v digital input voltage vind -0.3 dvdd+0.3 v operating ambient temperature ta -40 85 oc s torage temperature tstg -65 150 oc note 1. all indicated voltages are with respect to ground. note 2. vss1-5 must be connected to the same ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. (vss1=vss2=vss3=vss4=vss5=0v: note 1 ) parameter symbol min typ max units power supply voltage analog digital avdd dvdd 3.0 3.0 3.3 3.3 3.6 3.6 v v note 3. the power supply sequence for avdd and dvdd is no t critical but all power supplies must be on before start operating the AK7734. note 4. do not turn off the power supply of the AK7734 with the power supply of the surrounding device turned on. dvdd must not exceed the pull-up of sda and scl of i2 c bus. (the diode exists for dvdd in the sda and scl pins.) warning: akm assumes no responsibility for the usage beyond the conditions in the datasheet. absolute maximum ratings recommended operating conditions
[AK7734] ms1033-e-02-pb 10 2010/01 electric characteristics (1) analog characteristics 1) adc 1-1) fs=8khz (ta=25oc; avdd=dvdd=3.3v, bitclk=64fs; signal frequency 1khz; measurement frequency = 20hz~3.4khz @fs=8khz; ckm mode0(ckm[3:0]=llll) unless otherwise specified.) parameter min typ max units resolution 24 bits dynamic characteristics s/(n+d) (-1dbfs) 76 84 db dynamic range ( note 5 ) 84 92 db s/n 84 92 db inter-channel isolation (fin=1khz) ( note 6 ) 90 110 db dc accuracy channel gain mismatch 0.1 0.3 db analog input input voltage ( note 7 ) 1.85 2.00 2.15 vp-p adc section input impedance 38 58 k ? note 5. - s/(n+d) when -60db fs signal is applied. note 6. inter-channel isolation between ainr and ainl at ?1db fs signal input. note 7. full scale output voltage is fs=avdd2.0/3.3. 1-2) fs=48khz (ta=25oc; avdd=dvdd=3.3v, bitclk=64fs; signal frequency 1khz; measurement frequency =20hz~20khz @fs=48khz; ckm mode0(ckm[3:0]=llll) unless otherwise specified.) parameter min typ max units resolution 24 bits dynamic characteristics s/(n+d) (-1dbfs) 75 83 db dynamic range (filter a) ( note 8 ) 87 96 db s/n (filter a) 87 96 db inter-channel isolation (fin=1khz) ( note 9 ) 90 110 db dc accuracy channel gain mismatch 0.1 0.3 db analog input input voltage ( note 10 ) 1.85 2.00 2.15 vp-p adc section input impedance 23 35 k ? note 8. - s/(n+d) when -60dbfs signal is applied. note 9. inter-channel isolation between ainr and ainl at ?1db fs signal input. note 10. full scale output voltage is fs=avdd2.0/3.3.
[AK7734] ms1033-e-02-pb 11 2010/01 (2) src (ta=25oc; avdd = dvdd=3.3v; vss=0v, data = 24bit; meas urement bandwidth = 20hz~ fso/2; unless otherwise specified.) parameter symbol min typ max units resolution 24 bits input sample rate fsi 7.35 96 khz output sample rate fso 7.35 48 khz thd+n (input= 1khz, 0dbfs) fso/fsi=44.1khz/48khz fso/fsi=44.1khz/96khz fso/fsi=48khz/44.1khz fso/fsi=48khz/96khz fso/fsi=48khz/8khz fso/fsi=8khz/48khz fso/fsi=8khz/44.1khz -112 -104 -112 -112 -111 -113 -78 -103 db db db db db db db dynamic range (input= 1khz, -60dbfs) fso/fsi=44.1khz/48khz fso/fsi=44.1khz/96khz fso/fsi=48khz/44.1khz fso/fsi=48khz/96khz fso/fsi=48khz/8khz fso/fsi=8khz/48khz fso/fsi=8khz/44.1khz dynamic range (input= 1khz, -60dbfs, a-weighted fso/fsi=44.1khz/48khz 109 113 113 113 113 112 113 113 115 db db db db db db db db ratio between input and output sample rate fso/fsi 0.167 6 - (3) dc characteristics (ta=-40oc~85oc; avdd=dvdd=3.0~3.6v) parameter symbol min typ max units high level input voltage ( note 11 ) vih 80%dvdd v low level input voltage ( note 11 ) vil 20%dvdd v scl,sda high level input voltage vih 70%dvdd v scl,sda low level input voltage vil 30%dvdd v high level output voltage iout=-100 a voh dvdd-0.5 v low level output voltage iout=100 a ( note 12 ) vol 0.5 v sda low level output voltage iout=3ma vol 0.4 v input leak current ( note 13 ) input leak current (pull-down pin) ( note 14) input leak current (xti pin) iin iid iix 22 26 10 a a a note 11. scl and sda pins are not included. (sclk pins are included) note 12. sda pin is not included. note 13. pull-down pins, and the xti pin is not included. note 14. testi1 and testi2 pins are internal pulled-down pin. (typ150k ? )
[AK7734] ms1033-e-02-pb 12 2010/01 (4) current consumption (ta=25oc; avdd=dvdd=3.0~3.6v (when typ=3.3v, max=3.6v)) parameter min typ max units power supply current ( note 15 ) avdd dvdd avdd+dvdd initrstn pin= ?l? (reference) ( note 16) 21 65 86 2 120 ma ma ma ma note 15. the current of dvdd changes depending on th e system frequency and contents of the dsp program. note 16. this is a reference value when using a crystal oscillator. since most of the supply current at the initial reset state are in the oscillator section, the value may vary accord ing to the crystal type and the external circuit. this is a ?reference data? only.
[AK7734] ms1033-e-02-pb 13 2010/01 adc section 1. fs=8khz (ta=-40oc ~85oc, avdd=dvdd=3.0~3.6v, fs=8khz; note 17 ) parameter symbol min typ max units passband (0.1db) ( note 18 ) (-1.0db) (-3.0db) pb 0 3.63 3.83 3.15 khz khz khz stopband sb 4.66 khz passband ripple ( note 18 ) pr 0.1 db stopband attenuation ( note 19 , note 20) sa 68 db group delay distortion gd 0 p s group delay (ts=1/fs) gd 16 ts note 17. frequency of each amplitude characteristic is in propo rtion to fs (sampling rate). the characteristic of the high pass filter is not included. note 18. the passband is from dc to 3.15khz when fs=8khz. note 19. the stopband is 4.66khz to 507.34khz when fs=8khz. note 20. when fs = 8khz, the analog modulator samples the input signal at 512khz. there is no attenuation of an input signal in band (n x 512khz 4.66khz; n=0, 1, 2, 3?) of integer times of the sampling frequency by the digital filter. 2. fs=48khz (ta=-40oc~85oc, avdd=dvdd=3.0~3.6v, fs=48khz; note 17) parameter symbol min typ max units passband (0.1db) ( note 21 ) (-1.0db) (-3.0db) pb 0 20.0 23.0 18.9 khz khz khz stopband sb 28 khz passband ripple ( note 21) pr 0.04 db stopband attenuation ( note 22, note 23 ) sa 68 db group delay distortion gd 0 p s group delay (ts=1/fs) gd 16 ts note 21. the passband is from dc to 18.9khz when fs=48khz. note 22. the stopband is 28khz to 3.044mhz when fs=48khz. note 23. when fs = 48khz, the analog mo dulator samples the input signal at 5 12khz. there is no attenuation of an input signal in band (n x 3.072mhz 28khz; n=0, 1, 2, 3?) of integer times of the sampling frequency by the digital filter. digital filter characteristics
[AK7734] ms1033-e-02-pb 14 2010/01 system clock (ta=-40oc~85oc; avdd=dvdd=3.0~3.6v) parameter symbol min typ max units xti ckm[3:0]=0000, 0001, 0010 a) with a crystal oscillator: ckm[3:0]=0000 fs=44.1khz fs=48khz fxti - 11.2896 12.288 - mhz ckm[3:0]=0001 fs=44.1khz fs=48khz fxti - 16.9344 18.432 - mhz b) with an external clock duty cycle 40 50 60 % ckm[3:0]=0000, 0010 fs=44.1khz fs=48khz fxti 11.0 11.2896 12.288 12.4 mhz ckm[3:0]=0001 fs=44.1khz fs-48khz fxti 16.5 16.9344 18.432 18.6 mhz lrclki1 frequency ( note 24 ) fs 7.35 48 khz bitclki1 frequency a) ckm[3:0]=0010 64 fs high level width low level width tbclkh tbclkl 64 64 ns ns frequency fbclk 0.46 3.072 3.1 mhz b) ckm[3:0]=0011 ( note 25) 64 fs duty cycle 40 50 60 % frequency fbclk 2.75 3.072 3.1 mhz c) ckm[3:0]=0100 ( note 26) 32 fs duty cycle 40 50 60 % frequency fbclk 230 256 258 khz d) ckm[3:0]=0101 ( note 25) 64 fs duty cycle 40 50 60 % frequency fbclk 460 512 516 khz e) ckm[3:0]=1001 ( note 27) 48 fs duty cycle 40 50 60 % frequency fbclk 2.06 2.304 2.32 mhz f) ckm[3:0]=1010 ( note 27) 48 fs duty cycle 40 50 60 % frequency fbclk 345 384 387 khz lrclki2 frequency ( note 24 ) fs 7.35 48 khz bitclki2 frequency a) ckm[3:0]=1011 ( note 25 ) 64 fs duty cycle 40 50 60 % frequency fbclk 2.75 3.072 3.1 mhz b) ckm[3:0]=1100 ( note 26 ) 32 fs duty cycle 40 50 60 % frequency fbclk 230 256 258 khz c) ckm[3:0]=1101 ( note 25 ) 64 fs duty cycle 40 50 60 % frequency fbclk 460 512 516 khz note 24. lrck frequency and sampling rate (fs) should be the same. note 25. when bitclk is a source of master clock, it should be 64 times fs correctly. (64fs fixed) note 26. when bitclk is a source of master clock, it should be 32 times fs correctly. (32fs fixed) note 27. when bitclk is a source of master clock, it should be 48 times fs correctly. (48fs fixed) switching characteristics
[AK7734] ms1033-e-02-pb 15 2010/01 src input clock (ta=-40oc~85oc; avdd=dvdd=3.0~3.6v; vss=0v) parameter symbol min typ max units lrclki2 frequency fs 7.35 96 khz bitclki2 frequency frequency fbclk 0.23 3.072 6.144 mhz high level width tbclkh 32 ns low level width tbclkl 32 ns reset (ta=-40oc~85oc; avdd=dvdd=3.0~3.6v) parameter symbol min typ max units initrstn ( note 28 ) trst 600 ns note 28. it must be ?l? when power-up the AK7734.
[AK7734] ms1033-e-02-pb 16 2010/01 audio interface (sdin1-4, sdout1-4) (ta=-40oc~85oc; avdd=dvdd=3.0~3.6v, cl=20pf) parameter symbol min typ max units dsp section input sdin1-4 ( note 29 ) delay time from biclki1 ? ? to lrclki1 ( note 30 , note 31 ) tblrd 20 ns delay time from lrclki1 to bitclki1 ? ? ( note 30, note 31) tlrbd 20 ns serial data input latch setup time tbsids 80 ns serial data input latch hold time tbsidh 80 ns src section input sdin4 ( note 32 ) delay time from biclki2 ? ? to lrclki2 ( note 33) tblrd 20 ns delay time from lrclki2 to bitclki2 ? ? ( note 33) tlrbd 20 ns serial data input latch setup time tbsids 40 ns serial data input latch hold time tbsidh 40 ns output sdout1-4 ( note 29 ) bitclko frequency fbclk 64 fs bitclko duty factor 50 % delay time from bitclko ? ? to lrclko ( note 34 ) tblrd -20 40 ns delay time from lrclki1 to serial data output ( note 35 ) tlrd 80 ns delay time from bitclki1 to serial data output ( note 31 ) tbsod 80 ns delay time from lrclko to serial data output ( note 35 ) tlrd 80 ns delay time from bitclko to serial data output ( note 31 ) tbsod 80 ns sdinn sdoutn (n=1-4) ( note 36) delay time from sdinn to sdoutn output tiod 60 ns note 29. in ckm modeb/c/d, lrclki2=lrclki1, bitclki2=bitclki1. note 30. bitclki1 edge must not occur at the same time as lrclki1 edge. note 31. in pcm mode 0/2, bitclki1 is polarity reversal. note 32. except ckm mode b/c/d. note 33. bitclki2 edge must not occur at the same time as lrclki2 edge. when biedge bit= ?1?, this value is for bitclki2 ? ? since bitclk2 is polarity reversal. note 34. when selbck bit= ?1?, this value is for bitclko ? ? since bitclko is polarity reversal. note 35. except i 2 s. note 36. when sdin1 sdout1: control register setting seldo1[1:0] bit= ?01?, out1e bit= ?1? sdin2 sdout2: control register setting seldo2[1:0] bit = ?01?, out2e bit= ?1? sdin3 sdout3: control register setting seldo3[1:0] bit= ?01?, out3e bit= ?1? sdin4 sdout4: control register setting seldo4 bit= ?1?, out4e bit= ?1?
[AK7734] ms1033-e-02-pb 17 2010/01 microprocessor interface (ta=-40oc~85oc; avdd=dvdd=3.0~3.6v; vss=0v; cl=20pf) note 37. except for, when writing to 8th bit of command code. i 2 c bus interface (ta=-40oc~85oc; avdd=dvdd=3.0~3.6v) parameter symbol min typ max unit i 2 c timing scl clock frequency fscl 400 khz bus free time between transmissions tbuf 1.3 p s start condition hold time (prior to first clock pulse) thd:sta 0.6 p s clock low time tlow 1.3 p s clock high time thigh 0.6 p s setup time for repeated start condition tsu:sta 0.6 p s sda hold time from scl falling thd:dat 0 0.9 p s sda setup time from scl rising tsu:dat 0.1 p s rise time of both sda and scl lines tr 0.3 p s fall time of both sda and scl lines tf 0.3 p s setup time for stop condition tsu:sto 0.6 p s pulse width of spike noise suppressed by input filter tsp 0 50 ns capacitive load on bus cb 400 pf note 38. i 2 c-bus is a trademark of nxp b.v. parameter symbol min typ max units microprocessor interface signal rqn fall time twrf 30 ns rqn rise time twrr 30 ns sclk fall time tsf 30 ns sclk rise time tsr 30 ns sclk frequency fsclk 2.1 mhz sclk low level width tsclkl 200 ns sclk high level width tsclkh 200 ns microprocessor AK7734 rqn high level width twrqh 500 ns from rqn ? ? to sclk ? ? twsc 500 ns from sclk ? ? to rqn ? ? tscw 800 ns si latch setup time tsis 200 ns si latch hold time tsih 200 ns AK7734 microprocessor deley time from sclk ? ?to so output tsos 200 ns hold time from sclk ? ? to so output ( note 37 ) tsoh 200 ns
[AK7734] ms1033-e-02-pb - 18 - 2010/01 timing diagram figure 3. system clock figure 4. reset note 39. the initrstn pin must be ?l? when power-up/power-down the AK7734. 1/fxti 1/fxti vih vil xti 1/fs 1/fs vih vil lrclki1,2 tbclkl tbclkh 1/fbclk 1/fbclk vih vil bitclki1,2 tbclk=1/fbclk txti=1/fxti ts=1/fs vil trst initrstn
[AK7734] ms1033-e-02-pb - 19 - 2010/01 tbsids tblrd tlrbd vih lrclki1,2 bitclki1,2 vil vih vil vih vil tbsidh sdinn n=1,2,3,4 figure 5. audio interface (dsp section slave mode input) tbsids tblrd tlrbd vih lrclki2 vil vih vil vih vil tbsidh sdin4 bitclki2 figure 6. audio interface (src section input) figure 7. audio interface (slave mode output) tlrd vih lrclki1,2 bitclki1,2 vil vih vil sdoutn n=1,2,3,4 50%dvdd tbsod tlrd tbsod
[AK7734] ms1033-e-02-pb - 20 - 2010/01 figure 8. audio interface (master mode input) figure 9. audio interface (master mode output) figure 10. micropro cessor interface rqn vih vil twrf twr r sclk tsclkh tsclkl vih vil tsf ts r 1/fsclk 1/fsclk tbsids tmbl tmbl 50%dvdd lrclko bitclko vih vil tbsidh sdinn n=1,2,3,4 50%dvdd tlrd 50%dvdd lrclko bitclko sdoutn n=1,2,3,4 50%dvdd tbsod tlrd tbsod 50%dvdd
[AK7734] ms1033-e-02-pb - 21 - 2010/01 figure 11. microprocessor interface (microprocessor AK7734) figure 12. microprocessor interface (AK7734 microprocessor) figure 13. i 2 c bus interface rqn twr q h tsis tsih si vih vil vih twsc sclk tscw tscw twsc tscw vil vih vil sclk vil vih tsos tsoh so v o h v o l thigh scl sda vih tlow tbuf thd:sta t r tf thd:da t tsu:da t tsu:sta sto p start start sto p tsu:sto vil vih vil tsp
[AK7734] ms1033-e-02-pb - 22 - 2010/01 package 48pin lqfp (unit: mm) materials and lead specification package: epoxy lead frame: copper lead-finish: soldering (pb free) plate 12 48 13 7.00 9.00 0.20 7.00 9.00 0.20 0.19 0.05 0.10 s 37 24 25 36 0.17 0.05 1.4typ 0.10 0.07 1.60max 0 ? ~ 10 ? 0.10 m 0.50 0.20 0.50 1.00
[AK7734] ms1033-e-02-pb - 23 - 2010/01 marking a km a k7734xq xxxxxxx 1 revision history date (yy/mm/dd) revision reason page contents 09/03/24 00 first edition 09/11/16 01 description change 6, 7 digital ground 0v ground 0v analog ground 0v ground 0v error correction 13 digital filter characteristics note 20: ?n x 512khz 3.665khz? ?n x 512khz 4.66khz? note 23: ?n x 3.072mhz 21.99khz? ?n x 3.072mhz 28khz? 10/01/06 02 1) pin #1 indication 2) date code: xxxxxxx(7digits) 3) marking code: AK7734xq 4) asahi kasei logo
[AK7734] ms1033-e-02-pb - 24 - 2010/01 important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these products , please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z akm assumes no liability for infringement of any patent, intellect ual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of expor t pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to r esult, whether directly or indirectly, in the loss of th e safety or effectiveness of the device or system conta ining it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one design ed or intended for life support or maintenance of s afety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to func tion or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm pr oducts, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification. thank you for your access to akm product information. more detail product info rmation is available, please contact our sales office or authorized distributors.

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